The present invention is directed to integrated circuits and, more particularly, to a flip-flop cell with a configurable delay.
In integrated circuits (IC), clocked flip-flops are commonly used for propagating data through various data paths. Such flip-flops typically include master and slave latches using clock signals for receiving data inputs and propagating data within the IC, in functional mode of operation. Testability typically requires groups of the flip-flops to be connected, in scan test mode, into a serial scan register chain for loading and unloading scan test signals (test vectors).
Proper operation during either functional or test modes requires that the input data be valid without changing again at minimum during the setup time of the flip-flop before being captured at the clock signal edge, and that the input data of the flip-flop remain stable at minimum for a hold time after the clock signal edge for the flip-flop to reliably latch the data.
The maximum clock frequency at which an IC can operate is defined by the time taken to propagate data along the slowest path including logic and flip-flops. In functional mode, this operating frequency is often among the critical performance criteria of the IC. Among other factors, the setup time of flip-flops in some data propagation paths limits the maximum clock frequency. Slow operating frequency is a less important criterion for scan test operation and thus slower transistors can be used in the test data input paths to reduce hold time violations without the effect on setup time being a concern. Setup time problems for functional mode however can be improved by using different, faster transistors in the logic data path, but there is a limit on the speed that can be achieved.
Conventionally, buffers have been added to clock distribution paths to reduce setup time problems. However, the addition of a buffer to resolve setup time problems may degrade hold time violations. Also, the addition of a buffer incurs a penalty in terms of power consumption, chip area, and routing resources. This design problem arises only at the design stage of an IC but the penalties are incurred throughout the life of the IC.
While some slow sections of the functional data path may limit the timing performance, other sections may exhibit timing slack, that is to say that they perform better than the timing requirements. It is possible to borrow from the timing slack in a later section of the functional data path to improve the setup timing of an earlier section of the path.
It would be advantageous to have a way during the design process of flexibly configuring the slower and faster sections of the data paths to stably improve overall timing performance and with little or no penalty in terms of power consumption, chip area, and routing resources.